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Publications |
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Asynchronous VLSI |
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Parallel Architectures Low Latency Parallel Turbo Decoding |
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Theses |
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VLSI Architectures |
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High Speed Serial Links |
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1. |
R. Dobkin, M. Moyal, A. Kolodny, R. Ginosar, "Asynchronous Current Mode Serial Communication," IEEE Transactions on VLSI, 18(7), pp. 1107-1117, 2010. |
2. |
R. Dobkin, A. Morgenshtein, A. Kolodny, R. Ginosar, "Parallel vs. Serial On-Chip Communication," SLIP, pp. 43-50, 2008. |
3. |
R. Dobkin, A. Morgenshtein, A. Kolodny, R. Ginosar, "Parallel vs. Serial On-Chip Communication," CCIT TR674, EE Pub No. 1631, EE Dept., Technion, December 2007, www.ee.technion.ac.il/~ran/papers/parallelserial 2007.pdf. |
4. |
R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, A. Kolodny, "High Rate Wave-Pipelined Asynchronous On-Chip Bit-Serial Data Link," Proc. of ASYNC, pp. 3-14, 2007. |
5. |
R. Dobkin, R. Ginosar, A. Kolodny, "Fast Asynchronous Shift Register for Bit-Serial Communication," Proc. of ASYNC, pp. 117-126, 2006. |
6. |
R. Dobkin, R. Ginosar, A. Kolodny, "High-Speed Serial Interconnect for NoC," NoC Workshop, DATE, 2006. |
7. |
R. Dobkin, I. Cidon, R. Ginosar, A. Kolodny, A. Morgenshtein, "Fast Asynchronous Bit-Serial Interconnects for Network-on-Chip," CCIT TR529, EE Pub No. 1480, EE Dept., Technion, April 2005. |
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Synchronization |
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1. |
R. Dobkin, D. Alon, "Combining CDC Analysis and STA Tools for MCD SoC Verification," SNUG 2011. pdf presentation |
2. |
S. Beer, R. Ginosar, M. Priel, R. Dobkin, A. Kolodny, "An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm", Proc. of ISCAS, pp. 2593-2596, 2011. |
3. |
R. Dobkin, "Synchronization Issues in Multiple-Clock Domain Designs," ChipEx, 2010. |
4. |
S. Beer, R. Dobkin, M. Priel, R. Ginosar, A. Kolodny, "The Devolution of Synchronizers," Proc. of ASYNC, pp. 94-103, 2010. |
5. |
R. Dobkin, R. Ginosar, "Two Phase Synchronization with Sub-cycle Latency," VLSI Integration Journal, 42(3) , pp. 367-375, 2009, doi:10.1016/j.vlsi.2008.11.006 |
6. |
R. Dobkin, R. Ginosar, "Fast Universal Synchronizers," PATMOS, pp. 199-208, 2008 |
7. |
R. Dobkin, R. Ginosar, "Zero latency synchronizers using four and two phase protocols," CCIT TR642, EE Pub No. 1599, EE Dept., Technion, October 2007, www.ee.technion.ac.il/~ran/papers/zerolatency.pdf. |
8. |
R. Dobkin, R. Ginosar and C. P. Sotiriou, "High Rate Data Synchronization in GALS SoCs," IEEE Transactions on VLSI, 14(10), pp. 1063-1074, 2006. |
9. |
R. Dobkin, R. Ginosar, C. Sotiriou, "Data Synchronization Issues in GALS SoCs," Proc. of ASYNC, pp. 170-179, 2004. |
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Asynchronous NoC and Asynchronous Systems Verification |
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1. |
R. Dobkin, T. Kapshitz, S. Flur, R. Ginosar, "Assertion Based Functional Verification of Multiple-Clock GALS Systems", VLSI-SOC, pp. 152-155, 2008. |
2. |
R. Dobkin, T. Kapshitz, S. Flur, R. Ginosar, "Assertion Based Verification of Multiple-Clock GALS Systems", CCIT TR700, EE Pub No. 1657, June 2008. |
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R. Dobkin, R. Ginosar, A. Kolodny, "QNoC Asynchronous Router", Integration VLSI Journal, 42(2), pp. 103-115, 2009, doi:10.1016/j.vlsi.2008.03.001. |
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R. Dobkin, R. Ginosar, I. Cidon, "QNoC Asynchronous Router with Dynamic Virtual Channel Allocation," First ACM/IEEE Int. Symp. on Networks on Chip (NOCS), p. 218, 2007. |
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R. Dobkin, V. Vishnyakov, E. Friedman and R. Ginosar, "An Asynchronous Router for Multiple Service Levels Networks on Chip," Proc. of ASYNC, pp. 44-53, 2005. |
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Low Power |
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1. |
I. Schwartz, A. Teman, R. Dobkin, A. Fish, "Near-Threshold 40nm Supply Feedback C-Element," Proc. of ASQED, pp. 74-78, 2011 . |
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R. Dobkin, M. Peleg and R. Ginosar, "Parallel Interleaver Design and VLSI Architecture for Low-Latency MAP Turbo Decoders," IEEE Transactions on VLSI, 13(4), pp. 427–438, 2005. |
2. |
R. Dobkin, M. Peleg and R. Ginosar, "Parallel VLSI Architecture and Parallel Interleaver Design for Low-Latency MAP Turbo Decoders," CCIT TR436, EE Dept., Technion, July 2003. |
3. |
R. Dobkin, M. Peleg, R. Ginosar, "Parallel VLSI Architecture for MAP Turbo Decoder," Proc. of PIMRC, vol. 1, pp. 384-388, 2002. |
1. |
A. Tamam, R. Dobkin, O. Maltz, L. Zahavi, E. Pecht, M. Peleg, "Implementation of Interference Rejection for OFDM Communications," Israel IEEE Conf., 2010. |